The present disclosure relates to a semiconductor device, and in particular relates to power source control of the semiconductor device which includes an active mode and a standby mode as operation modes.
The semiconductor device such as a microcomputer and so forth includes a power source circuit adapted to generate a power source voltage (hereinafter, also referred to as an internal power source voltage) to be supplied to an internal circuit. In the semiconductor devices so configured, one semiconductor device which is configured to switch a power source circuit to be operated depending on whether the semiconductor device is in operation (in the active mode) or is put on standby (in the standby mode) is widely used in order to implement high-speed operation and low power consumption.
It is necessary for the power source circuit to generate a stable power source voltage in the both operation modes of the active mode and the standby mode of the semiconductor device. For this purpose, in the active mode that the power consumption is high and a voltage drop is liable to occur, a power source circuit which is high in power supplying capability is used, while in the standby mode that the power consumption is low, a power source circuit which is reduced in power consumption is used for implementing low power consumption.
In a chip with multiple power sources, it is necessary to sequentially rise a plurality of power source voltages in accordance with a power source start-up sequence which has been defined in advance so as not to cause such a defect that respective circuits are biased in a forward direction in power-on. Control of this power source start-up sequence imposes restrictions on users.
In this respect, a configuration that a switch circuit is provided so as not to cause the defect that the circuits are biased in the forward direction regardless of the power on sequence is disclosed (see Japanese Unexamined Patent Application Publication No. 2014-130406).
Specifically, there is proposed the switch circuit configured to short-circuit a supply path of a power source voltage to a memory cell of a memory array and a supply path of a power source voltage for a peripheral circuit in the active mode and to supply only the power source voltage to the memory cell of the memory array and to shut down the supply path of the power source voltage for the peripheral circuit in the standby mode.